LogicSimulator
Neelakantam, Naveen and Greskamp, BrianLogicSimulator is a graphical schematic editor and simulator for digital logic circuits intended as a teaching tool for introducting students to the fundamentals of digital design. The interface is simple and intuitive, yet powerful. Starting from a small library of built-in components, students construct new components build their libraries. By bootstrapping his own component library from the ground up, the student learns the fundamentals of hierarchical design.
LogicSimulator makes it easy to visualize circuit operation. All wires and pins are color coded by logic level, so the user can tell the current value at a glance. Simulation speed is variable, with gate delays ranging from milliseconds to seconds. LogicSimulator also includes the ability to pause and single-step simulations, useful for logic debugging. The user can even "expand" subcircuits as the simulation runs to observe internal signals.
Quick Start
Load CS598REJ-LogicSimulator.st into your browser and execute "PaletteWindow open". This will display the Palette, which holds all tools and components. Click on the "new circuit" button to create a circuit. Select the "Place" tool and the "NOR" component. Click in the circuit canvas to place the NOR gate. Now select the "Switch" component and click twice on the circuit canvas to place two switches.
Note that the input and output pins on the NOR gate are black. This indicates that they have an "undefined" logic level because the inputs aren't connected to anything. To connect the NOR gate inputs to the switches, select the "Connect" tool. To draw a connection, click on the source pin then click on the destination pin. If you make a mistake, you can delete components or connections with the "Delete" tool.
Once the switches are connected, the NOR gate's output should no longer be undefined. Click on the switch buttons to toggle the switches and note how the NOR output color changes. If you haven't guessed, red is logic "0" and green is logic "1".
Play with the simulation speed and stepping controls in the upper right of the circuit window and notice how they affect the simulation. Of course a single NOR isn't very interesting. Place a D Flip-flop ("DFF") and connect switches to its D and CLK inputs. Note how the flip flop responds; it is a falling edge triggered flip flop. To see what is going on inside of the DFF component, select the "Expand" tool and click on the DFF instance in the circuit window. Now, as the simulation runs, you can observe all of the internal connections inside the flip-flop.
Next, let's add a new subcircuit to our palette of components. Draw a simple circuit. Before adding it to the palette, we need to define the inputs and outputs for our new subcircuit. The first step is to use the "New Pin" tool to create a labelled pin for each input and each output. Select the tool and click in the circuit canvas where you want to place the pin. You will be prompted to enter a name. Now connect the pin you just placed to the appropriate gate input or output. The placement of the pins determines how the "black box" view of your subcircuit will be rendered when you instantiate it in a new circuit. So you should use the "Move" tool to position pins where you want them.
Now we can add the circuit to the palette by clicking the "Palettize"
button in the circuit window. We can also save it to disk by clicking "Save". We can open previously saved circuits using the "Open" button on the palette. It should now be clear how to build arbitrarily complex circuit hierarchies in LogicSimulator. Have fun!
Background + Related
Squeak has the start of a framework for placing and wiring together dataflow functions. It is part of the "Fabrik" framework by Dan Ingalls: http://users.ipa.net/~dwighth/smalltalk/Fabrik/Fabrik.html. The key issue is whether it's just easier to write what we need from scratch, and I think it is.
The logic simulation engine is based on a simplification of the classic "event queue" approach (e.g. http://www-ee.eng.hawaii.edu/~msmith/ASICs/HTML/Book/CH13/CH13.4.htm). Since we assume all gates have the same delay, it is possible to eliminate the queue and replace it with a list of events scheduled for the next simulator tick.
Need to look into automatic wire routing algorithms so that if the user selects two pins to connect, the application automatically draws a line with right angle turns that doesn't pass over gate icons.
Link to this Page
- Class projects last edited on 2 April 2008 at 5:20:59 pm by vpn3-144241.near.uiuc.edu